不論順序的先後,是否要結合在一起 都有著不同的想法
也能從遠先兩兩不能結合在一起的COMPUTE
結合起來卻能夠互相彌補而成為正確的方塊圖!!
程式碼也得開始進行,試試看原先的除法器:

`define NUM_STATE_BITS 3
`define IDLE 3'b000
`define INIT 3'b001
`define COMPUTE1 3'b010
`define COMPUTE2 3'b011
`define COMPUTE3 3'b100
module cl(clk);
parameter TIME_LIMIT = 110000;
output clk;
reg clk;
initial
clk = 0;
always
#50 clk = ~clk;
always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;
endmodule
module slow_div_system(pb,ready,x,y,r3,sysclk);
input pb,x,y,sysclk;output ready,r3;
wire pb;wire [11:0] x,y;reg ready;
reg [11:0] r1,r2,r3;
reg [`NUM_STATE_BITS-1:0] present_state;
always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x;
r2 <= @(posedge sysclk) 0;ready = 1;
if (pb)
begin
while (r1 >= y)
begin
@(posedge sysclk) enter_new_state(`COMPUTE1);
r1 <= @(posedge sysclk) r1 - y;
@(posedge sysclk) enter_new_state(`COMPUTE2);
r2 <= @(posedge sysclk) r2 + 1;
@(posedge sysclk) enter_new_state(`COMPUTE3);
r3 <= @(posedge sysclk) r2 ;
end
end
end
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